Direct data sample single tone receiver



K. H. RENSHAW DIRECT DATA SAMPLE SINGLE TONE RECEIVER B F/G 6 TOGGLE F/7 I TOGGLE F/G 8 SET RESET SET RESET F/G' .9 EXCLUSIVE OR GATE 2Sheets-Sheet :3

INVENTOR.

KENNETH H RENSHAW ATTORNEYS Unite States Patent Ofiice 3,377,560Patented Apr. Q, 1968 3,377,560 DIRECT DATA SAMPLE SINGLE TONE RECEIVERKenneth H. Renshaw, Costa Mesa, Calif., assignor to (Iollins RadioCompany, Cedar Rapids, Iowa, a corporation of Iowa Filed Jan. 13, 1964,Ser. No. 337,478 4 Claims. (Cl. 325-320) ABSTRACT OF THE DISCLOSUREMeans for decoding an FSK signal employing one-half cycle frequency ffor a space and a full cycle of frequency 2 for a mark, by sampling thesignal at each bit transition time to produce a train of positive andnegative samplings.

In essence, the pulse train is delayed one bit period and then comparedwith the undelayed train. Coincidence indicates a mark andnon-coincidence indicates a space.

This invention relates generally to frequency shift keyed (FSK)receivers and, more specifically, to a receiver for decoding aparticular type FSK signal by an improved direct sampling datatechnique.

One form of communicating intelligence is to encode the intelligence inbinary form and then represent the marks and spaces by two differentfrequencies. The transmission of the intelligence can be in a timesynchronous manner in which each data bit occupies an interval of timeequal to that occupied by every other data bit with the time intervalsoccurring consecutively. One form of FSK encoding has been the use of ahalf cycle of one frequency and a full cycle of another frequency,one-half that of the first frequency, to designate marks and spaces. Forexample, the full cycle can designate a mark and the half cycle candesignate a space. When the full cycle designating a mark occurs, therewill be no change of potential over the entire full cycle, i.e., thepotential of the full cycle will be the same at the end as at thebeginning thereof. Thus, if the full cycle begins at a negative orpositive peak, it will end at a negative or positive peak. However, thehalf cycle representing a space will result in a change of polarity overthe occurrence of the half cycle (assuming the half cycle to begin at apositive or negative peak). It is this characteristic of a change inpolarity for a half cycle and a lack of change of polarity for a fullcycle that is employed to decode the FSK signal and to determine whethera mark or a space is represented during any bit period. By causing thetransition from one frequency to another at peak voltages, eitherpositive or negative, the transition between the frequencies is smoothand provides a minimum of distortion. A system for generating an FSKsignal of this type is described in detail in United States Patent3,102,- 238 issued Aug. 27, 1963 to Lynn R. Bosen, entitled Encoder WithOne Frequency Indicating One Binary Logic State and Another FrequencyIndicating Other State, incorporated by reference herein.

One system which has been developed for decoding such an FSK signal isdescribed in co-pending application Ser. No. 150,786, filed Nov. 7,1961, entitled Single Tone Data Receiver, by Kenneth H. Renshaw andincorporated herein by reference. Such application is believed toconstitute the closest prior art to the present invention. In suchco-pending application the information is decoded generally by firstheterodyning the received FSK signal to a higher frequency and thensupplying the heterodyned signal into a balanced discriminator whichfunctions to produce an output signal which rises and falls between twolevels with one level representing marks and the other levelrepresenting spaces. Such output signal is then sampled and thesamplings supplied to a flip-flop circuit which responds thereto toassume one or the other of its two states, thus producing a two-levelbinary signal representing the marks and spaces contained in thereceived FSK signal. In such prior art, however, it will be noted thatit was necessary to heterodyne the received FSK signal to a higherfrequency and then to pass it through a balanced discriminator in orderto produce a two-level signal which could be sampled with the samplings,and then be employed to drive a flip-flop circuit.

An object of the present invention is to provide an FSK receiver whichis less expensive and simpler than FSK signal receivers of the priorart.

A second purpose of the invention is to provide an FSK signal receiverwhich will sample the received FSK signal directly without the necessityof heterodyning it to a higher frequency and then passing it through abalanced discriminator.

A third aim of the invention is the improvement of FSK signal receivers,generally.

In accordance with the present invention, the received FSK signal issupplied to a means for extracting a synchronizing signal therefrom andalso is supplied to a sampling or gating circuit. The synchronizingsignal is employed to generate sampling pulses which are also suppliedto said sampling circuit to sample the received FSK signal at thebeginning of each data bit. The beginning of one data bit period, ofcourse, is the end of the preceding bit.

Thus, a series of samplings will be obtained. If the bit being sampledis a mark, then the polarity of a sampling at the beginning and end ofsuch bit will be the same, i.e., either positive or negative. On theother hand, if the polarity of the samplings at the beginning and of anygiven bit change, the presence of a space is indicated. Means aresupplied to separate the positive samplings from the negative samplingsand to supply them to the set and reset inputs of a toggle switch or aflip-flop circuit. A second toggle switch or flip-flop circuit isresponsive to the first flip-flop circuit to store therein the conditionof the first flip-flop circuit during the immediately preceding bitperiod. Thus, if the states of the two toggle switches are the same,this indicates that no change in polarity has occurred and that a markhas just been received. If the states of the two toggle switches aredifferent, a change of polarity has occurred indicating that a space hasjust been received. An exclusiveOR circuit is responsive to the setoutputs of the two toggle switches and functions to indicate whether theconditions of the two toggle switches are the same or different, andthereby produce a two-level binary signal containing the data of thereceived FSK signal.

In accordance with a particular feature of the invention there isrequired no heterodyning of the received FSK signal to a higher signaland no need for a balanced discriminator, as in the prior art. Thereceived FSK signal is sampled directly, thus resulting in a lessexpensive and more reliable FSK type receiver.

The aforementioned objects and features of the invention will be morefully understood from the following detailed description thereof whenread in conjunction with the drawings in which:

FIG. 1 is a block diagram of the invention;

FIG. 2 is a waveform of the received FSK signal;

FIG. 3 shows the sampling pulses derived from the received FSK signal;

FIG. 4 shows the samplings of the received FSK signal;

FIGS. 5 and 6 show the samplings of FIG. 4 separated in accordance withpolarity;

FIGS. 7 and 8 show the conditions of the two toggle switches in responseto the samplings of FIGS." and 6 being supplied thereto; and

FIGS. 9 and 10 show the resultant two-level binary signal with the curveof FIG. 10 being an inversion of the curve of FIG. 9.

Referring now to FIG. 1, the FSK signal of FIG. 2 is supplied fromsource 10 over a suitable transmitting medium such as wire lines 11 to aline transformer 12.

It is to be understood that means other than wire line transmissionmeans can be employed to supply the signal from source 10 to thereceiver. The signal can be trans mitted through space on a carriersignal, in which case the receiver must be provided with means forrecovering the FSK signal from the modulated carrier. In the particularembodiment shown in FIG. 1, a carrier is not required since the, signalis transmitted over wire lines, such as telephone lines.

From the line transformer the signal is supplied to an automatic gaincontrol (AGC) amplifier 13- which functions to amplify the signal and toprovide a constant level input signal, as shown in FIG. 2. The output ofthe amplifier 13 is supplied to two circuits substantially in parallel.One of these circuits includes a synchronizing demodulator circuit 24, a2400 c.p.s. oscillator 25, pulse positioning one-shot multi-vibrator 26,and a sample pulse generator 27. The function of the circuit set forthimmediately above is to generate a train of sampling pulses, as shown inFIG. 3, the purpose of which will be described in more detail laterherein.

The second circuit to which the output of the amplifier 13 is suppliedconsists of the gating circuit 14, a phase splitting amplifier 15,shaping amplifiers 16 and 17, and toggle switches '18 and 19 whichtogether form a twostage shift register. The output of the two toggleswitches is supplied to an exclusive OR gate 20 through leads 22 and 23.The OR gate functions as a modulo two adder with its output supplied toinverter circuit 21. The output of inverter circuit 21, shown in FIG.10, is a twolevel signal containing the data in the received FSK signaland having the polarity of the two-level binary signal from which theFSK signal was originally derived.

In the particular circuit of FIG. 1, let it be assumed that the twofrequencies being employed to represent marks and spaces are a 2400c.p.s. signal and a 1200 c.p.s. signal with a full cycle of the 2400cycle signal representing a mark and a half cycle of the 1200 cps.signal representing the space. Thus, in FIG. 2, for example, the halfcycle represented between times t and 1 of FIG. 2 is a half cycle of a1200 c.p.s. signal and represents a space. Similarly, the full cycle ofFIG. 2 shown during the time interval t t is a full cycle of the 2400c.p.s. signal and represents a mark. it will be observed that thetransition between the half-cycle of the 1200 c.p.s. signal and the fullcycle of the 2400 c.p.s. signal ocurs at the peak amplitude shown attime 1 It will be noted that at the other times noted, such as times t tt t t and t transfers will occur. from one bit to the next succeedingbit which in many cases will be a transfer from one frequency to theother frequency, with all of said transfers ocurring at either apositive or negative peak of the two signals.

Referring again to the sampling pulse generating circuit of FIG. 1, thesynchronizing signal demodulator block 24 functions to respond to thewaveform of FIG. 2 to produce a 2400 c.p.s. signal. The specific meansby which the demodulator 24 of FIG. 1 functions is described in detailin the aforementioned co-pending application, Ser. No. 105,786. Theoutput of the synchronizing signal generator 24 is employed to drive the2400 c.p.s. oscillator.25. The oscillator 25 is constructed to supply asquarewave output to pulse positioning one-shot circuit 26 which, inessence, is a delaying circuit. More specifically, one shot pulsepositioning circuit 26 functions to change the phase of the output ofoscillator 25 so that the pulses generated in the samplepulse'gen'erator 27 will occur at the optimum sampling times of the FSKwaveform of FIG. 2. The optimum sampling times occur when the FSKwaveform of FIG. 2 is at its maximum value. Such optimum times areindicated by the time reference characters t t in FIG. 2.

The sampling pulses of FIG.3, which are produced at.

the output of the sample pulse generator 27,are supplied both to thegating circuit 14 and to. the toggle switch 18 of FIG. 1. The samplingpulses supplied to the gating circuit 14 function to sample the FSKsignal of FIG. 2 during each transition period. FIG. 4represents theoutput of the gating circuit 14 and can be seen to consist of a seriesof negative and positive pulses with the negative pulses resulting froma sampling of the FSK signal during negative peaks and the positivepulses resulting from a sampling of the FSK signal during positivepeaks.

The output of gating circuit 14 is supplied to phase split amplifier 15which separates the positive pulsesfrom the negative pulses and suppliesthe separated pulses to shaping amplifiers 1'6 and 17; Morespecifically, the phase split amplifier 15 supplies the positive pulsesto shaping amplifier 16 and inverts the negative pulses and suppliessaid inverted negative pulses to shaping amplifier 17. The

waveforms of FIG. 5 and FIG. 6 represent the pulses supplied to theshaping amplifiers 16 and 17, respectively, from phase. splittingamplifier 15.

Shaping amplifiers 116 and 17 amplify and shape the pulses to a suitablemagnitude and sharpness. The shaped pulses are then supplied to the twoinput leads of toggle switch 18, which has a set and a reset positionand is, in effect, a two-input flip-flop circuit. For purposes ofdiscussion, assume that a pulse from shaping amplifier 16 will causetoggle switch 18 to assume its set position and a pulse from the shapingamplifier 17 will cause toggle switch. 18 to assume its reset position.

The waveform of FIG. 7 represents the state of the toggle switch 18 inresponseto the FSK signal of FIGQ2 with the upper level of FIG. 7representing the set condition and the lowerlevel representing the resetcondition. Also, the waveform of FIG. 7 representsthe signal 1 appearingon the output lead 22 of toggle switch 18.

A second toggle switch or flip-fiop circuit 19 is connected to theoutput terminals of toggle switch 18 and also has two stable states. Thetwo switches 18 and 19 together form a two-stage shift register. Since,shift registers are well known in the art, they will not be discussed indetail herein. The condition of toggle switch 18 is shifted to toggleswitch 19 by the sampling pulse via lead 29 immediately before the newcondition of toggle switch 18 is effected/Consequently, the stage oftoggle switch 19 will always be representative of the bit immediatelypreceding the one currently being received and represented by toggleswitch 18. Thus, for example, in FIG. 8, which represents the output oftoggle switch 19 on lead 23, the set condition existing during timeinterval tg-[g (FIG. 8) was derived from the set condition of thepreceding bit contained in toggle switch 18 during the time interval t-t An examination of FIG. 7 and FIG. 8 will show that the waveform ofFIG. 8 lags the waveform of FIG. 7 by approximately one data bitinterval.

Further, it willbe seen from FIGS. 7 and 8 that if the levels of the twosignals shown therein are different during any given time interval, thenthe bit ofthe preceding time interval was a space, and if the levels ofthe two signals of FIGS7 and 8 are the same during any bit period, thatthe preceding bit was a mark. For example, during the time intervals t tthe levels of FIGS. 7 and 8 are different so that the preceding bit oftime interval t t was a space. During the time intervals 1 ,-t thelevels of the two signals of FIGS. 7 and 8 are the same indicating thatthe preceding bit of time: interval 1 4 was a mark, asis verified inFIG. 2.

The function of the exclusive OR gate 20, also known as a modulo twoadder is to produce an output when the levels of the signals on its twoinput leads 22 and 23 are the same, whether they are low level or highlevel signals. In FIG. 9 there is shown the waveform of the output ofthe exclusive OR gate of FIG. 1. It will be noted that the waveform ofFIG. 9 is a two-level signal. The circuit is designed so that the upperlevel of FIG. 9 represents the occurrence of similar levels on inputleads 22 and 23 of OR gate 20, and the lower level of FIG. 9 representsthe occurrence of dissimilar levels on input leads 22 and 23. Due to thedesign of the OR gate 20, the output thereof happens to be an inversionof the original two-level binary signal from which the FSK signal fromsource 10 was derived at the transmitter end of the system which is notdescribed herein. Consequently, it is necessary to invert the waveformof FIG. 9 by means of inverter 21 of FIG. 1. The output of inverter 21is shown in FIG. 10 and represents the original two-level binary signalfrom which the FSK signal was derived.

It is to be noted that the form of the invention shown and describedherein is but a preferred embodiment thereof and that various changesmay be made in circuit arrangement without departing from the spirit orthe scope thereof.

I claim:

1. In a communication system employing a time synchronous data carryingsignal in which a half Wave cycle of a signal of frequency f representsa binary bit 0, in which a full wave cycle of a signal of frequency 211represents a binary bit 1, in which the peak amplitude of said half andfull wave cycles are substantially equal, and in which the transitionfrom any given data bit to the next data bit always occurs at the peakamplitudes of the half and full wave cycles;

demodulating means comprising:

means for sampling the received data carrying signal substantially ateach bit transition time to produce a serial train of pulses consistingof positive pulses of substantially constant amplitude and negativepulses of substantially constant amplitude, one of said positive ornegative pulses occurring at each sampling time to indicate the polarityof the received data signal;

pulse separating means comprising fir t and second output terminal meansand constructed to supply all of said positive pulses to said firstoutput terminal means and all of said negative pulses to said secondoutput terminal means with the same time spacing said pulses maintainedin said train of pulses;

shift register means having a first stage and a second stage with eachstage having a set and reset state;

said first stage responsive to output pulses appearing on said first andsecond output terminal means of said pulse separating means to assumeits reset and its set condition, respectively;

said shift register means further constructed to shift the state of saidfirst stage into said second stage one bit period after the state ofsaid first stage is effected;

and exclusive OR circuit means responsive to the states of the stages ofsaid shift register means to produce a two-level binary signalrepresentative of the data contained in the received data carryingsignal.

2. Demodulating means in accordance with claim 1 in which said means forsampling the received data carrying signal comprises:

synchronizing signal generating means responsive to said received datacarrying signal to produce a signal having a frequency equal to the bitrate of said received data carrying signal;

and means responsive to said synchronizing signal to generate samplingpulses.

3. In a communication system employing a time synchronous data carryingsignal in which a half wave cycle of a signal of frequency f representsa binary bit 0, in which a'full wave cycle of a signal of frequency 2frepresents a binary bit 1, in which the peak amplitudes of said half andfull Wave cycles are substantially equal, and in which the transitionfrom any given data bit to the next data bit always occurs at the peakamplitudes of the 0 half and full wave cycles;

demodulating means comprising:

means for sampling the received data carrying signal substantially ateach bit transition time to produce a train of pulses consisting ofpositive pulses of substantially constant amplitude and negative pulsesof substantially constant amplitude, one of said positive or negativepulses occurring at each sampling time to indicate the polarity of thereceived data signal; pulse separating means comprising first and secondoutput terminal means and constructed to supply all of said positivepulses to said first output terminal means and all of said negativepulses to said second output terminal means with the same time spacingsaid pulses maintained in said train of pulses; first bistable meanshaving set and reset input and output terminal and responsive to theseparated positive and negative sampled pulses from said pulseseparating means to assume set and reset conditions accordingly; secondbistable means having set and reset input terminals and set outputterminal means and responsive to the output signals of said firstbistable means to assume the same conditions as said first bistablemeans but delayed by one bit period; and exclusive OR circuit meansresponsive to the set output signals of said first and second bistablemeans to produce a two-level signal binary representation of thereceived data with one level thereof representing binary 0s and theother level thereof representing binary 1s. 4. Demodulating means inaccordance with claim 3 in which said means for sampling the receiveddata carrying signal comprises:

synchronizing signal generating means responsive to said received datacarrying signal to produce a synchronizing signal having a frequencyequal to the bit rate of said received data carrying signal, and meansresponsive to said synchronizing signal to generate sampling pulses.

References Cited UNITED STATES PATENTS 2,939,914 6/1960 Ingham 178673,238,299 3/1966 Lender 178-68 3,112,448 11/1963 McFarlane et al. 178-66X ROBERT L. GRIFFIN, Primary Examiner.

DAVID G. REDINBAUGH, JOHN W. CALDWELL, Examiners. W. S. FROMMER,Assistant Examiner.

